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| Preliminary Information DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX CONTROL XR16C2850 DESCRIPTION The XR16C2850 (2850) is a dual universal asynchronous receiver and transmitter (UART). The 2850 provides enhanced UART functions with 128 byte FIFO, automatic RS-485 half duplex control, a modem control interface, and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 1.5 Mbps. The baud rate generator can be configured for either crystal or external clock input. The 2850 is available in a 40-pin PDIP, 44-pin PLCC, and 48-pin TQFP packages. The 40 pin package does not offer TXRDY and RXRDY pins (DMA Signal monitoring). Otherwise the three package versions are the same. The 2850 is functionally compatible with the ST16C2550. The 2850 is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. FEATURES * Pin and functionally compatible to ST16C2550, software compatible with INS8250, NS16C550 * 1.5 Mbps transmit/receive operation (24 MHz Max.). * 128 byte transmit FIFO to reduce bandwidth requirement of the external CPU. * 128 byte receive FIFO with error flags to reduce bandwidth requirement of the external CPU. * Independent transmit and receive UART control. * RS-485 half duplex control. * Programmable transmit/receive FIFO trigger levels. * Hardware / software flow control. * Selectable RTS flow control hysterisis. * Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break). * Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity. * Infrared receive and transmit encoder/decoder. * Device identification. * Crystal or external clock input. * 460.8 Kbps transmit/receive operation with 7.3728 MHz crystal or external clock source. PLCC Package -TXRDYA -DSRA 41 -CTSA 40 -CDA 42 VCC 44 D5 D6 D7 RXB RXA -TXRDYB TXA TXB -OPB -CSA -CSB 7 8 9 10 11 12 13 14 15 16 17 XTAL1 18 XTAL2 19 -IOW 20 -CDB 21 GND 22 -RXRDYB 23 -IOR 24 -DSRB 25 -RIB 26 -RTSB 27 -CTSB 28 43 6 5 4 3 2 1 -RIA D4 D3 D2 D1 D0 39 38 37 36 35 RESET -DTRB -DTRA -RTSA -OPA -RXRDYA INTA INTB A0 A1 A2 XR16C2850CJ 34 33 32 31 30 29 ORDERING INFORMATION Part number XR16C2850CP XR16C2850CJ XR16C2850CM 40 44 48 Pins Package PDIP PLCC TQFP Operating temperature 0 C to + 70 C 0 C to + 70 C 0 C to + 70 C Part number XR16C2850IP XR16C2850IJ XR16C2850IM 40 44 48 Pins Package PDIP PLCC TQFP Operating temperature -40 C to + 85 C -40 C to + 85 C -40 C to + 85 C Rev. 1.00P EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 XR16C2850 Figure 1, Package Descriptions, 40 pin, 48 pin XR16C2850 48 Pin TQFP Package 40 Pin DIP Package -RSCTL -DSRA -CTSA -CDA VCC N.C. -RIA D4 D3 D2 D1 D0 D0 D1 36 35 34 33 32 RESET -DTRB -DTRA -RTSA -OPA N.C. INTA INTB A0 A1 A2 N.C. 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 33 VCC -RIA -CDA -DSRA -CTSA RESET -DTRB -DTRA -RTSA -OPA INTA INTB A0 A1 A2 -CTSB -RTSB -RIB -DSRB -IOR 48 47 46 45 44 43 42 41 40 39 38 37 D5 D6 D7 RXB RXA N.C. TXA TXB -OPB -CSA -CSB N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D2 D3 D4 D5 D6 D7 RXB RXA TXA TXB -OPB -CSA -CSB XTAL1 XTAL2 -IOW -CDB GND XR16C2850CM 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 XR16C2850CP 32 31 30 29 28 27 26 25 24 23 22 21 XTAL1 XTAL2 -DSRB -IOW GND -IOR N.C. -RTSB Rev. 1.00P 2 -CTSB -CDB N.C. -RIB XR16C2850 Figure 2, Block Diagram D0-D7 -IOR -IOW RESET Data bus & Control Logic Transmit FIFO Registers Transmit Shift Register TX A/B TXIR A/B Flow Control Logic Inter Connect Bus Lines & Control signals Receive FIFO Registers Ir Encoder Receive Shift Register A0-A2 -CS A/B -RSCTL Register Select Logic RX A/B RXIR A/B INT A/B -RXRDY A/B -TXRDY A/B Interrupt Control Logic Flow Control Logic Ir Decoder -DTR A/B -RTS A/B Clock & Baud Rate Generator XTAL1 XTAL2 Modem Control Logic -CTS A/B -RI A/B -CD A/B -DSR A/B Rev. 1.00P 3 XR16C2850 SYMBOL DESCRIPTION Symbol A0 A1 A2 -CS A-B 40 28 27 26 14,15 Pin 44 31 30 29 16,17 48 28 27 26 10,11 Signal type I I I I Pin Description Address-0 Select Bit. - Internal register address selection. Address-1 Select Bit. - Internal register address selection. Address-2 Select Bit. - Internal register address selection. Chip Select A, B (active low) - This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the 2850 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective -CS AB pin. Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt A, B (three state) - This function is associated with individual channel interrupts, INT A-B. INT A-B are enabled when MCR bit-3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. Read strobe (active low strobe) - A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the 2850 data bus (D0-D7) for access by an external CPU. Write strobe (active low strobe) - A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. D0-D7 1-8 2-9 44-48 1-3 I/O GND INT A-B 20 30,29 22 33,32 17 30,29 Pwr O -IOR 21 24 19 I -IOW 18 20 15 I Rev. 1.00P 4 XR16C2850 SYMBOL DESCRIPTION Symbol -OP2 A-B 40 31,13 Pin 44 35,15 48 32,9 Signal type O Pin Description Output -2 (User Defined) - This function is associated with individual channels, A through B. The state at these pin(s) are defined by the user and through the software setting of MCR register bit-3. INT A-B are set to the active mode and OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are set to the three state mode and OP2 to a logic 1 when MCR3 is set to a logic 0. See bit-3, Modem Control Register (MCR bit-3). Reset (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time (see XR16C2850 External Reset Conditions for initialization details). Receive Ready A-B (active low) - This function is associated with 44 pin PLCC and 48 pin TQFP packages only. This function provides the RX FIFO/RHR status for individual receive channels (A-B). RXRDY is primarily intended for monitoring DMA mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is receive data to read/ unload, i.e., receive ready status with one or more RX characters available in the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed trigger level has not been reached. This signal can also be used for single mode transfers (DMA mode 0). Transmit Ready A-B (active low) - This function is associated with 44 pin PLCC and 48 pin TQFP packages only. These outputs provide the TX FIFO/THR status for individual transmit channels (A-B). TXRDY is primarily intended for monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual channels -TXRDY A-B buffer ready status is indicated by logic 0, i.e., at least one location is empty and available in the FIFO or THR. This pin goes to a logic 1 when there are no more empty locations in the FIFO or THR. This signal can also be used for single mode transfers (DMA mode 0). Power supply input. RESET 35 39 36 I -RXRDY A-B - 34,23 31,18 O -TXRDY A-B - 1,12 43,6 O VCC Rev. 1.00P 40 44 42 Pwr 5 XR16C2850 SYMBOL DESCRIPTION Symbol XTAL1 40 16 Pin 44 18 48 13 Signal type I Pin Description Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This configuration requires an external 1 MW resistor between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to provide custom data rates (see Baud Rate Generator Programming). Output of the Crystal Oscillator or Buffered Clock - (see also XTAL1). Crystal oscillator output or buffered clock output. Should be left open if an external clock is connected to XTAL1. Carrier Detect (active low) - These inputs are associated with individual UART channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. Clear to Send (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the 2850. Status can be tested by reading MSR bit-4. This pin has no effect on the UARTs transmit or receive operation. Data Set Ready (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UARTs transmit or receive operation. Data Terminal Ready (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the 2850 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This XTAL2 17 19 14 O -CD A-B 38,19 42,21 40,16 I -CTS A-B 36,25 40,28 38,23 I -DSR A-B 37,22 41,25 39,20 I -DTR A-B 33,34 37,38 34,35 O Rev. 1.00P 6 XR16C2850 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description pin has no effect on the UARTs transmit or receive operation. -RI A-B 39,23 43,26 41,21 I Ring Indicator (active low) - These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. Request to Send (active low) - These outputs are associated with individual UART channels, A through B. A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UARTs transmit or receive operation. Receive Data (A-B) - These inputs are associated with individual serial channel data to the 2850 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the RX input pin is disabled and TX data is connected to the UART RX Input, internally. Transmit Data (A-B) - These outputs are associated with individual serial transmit channel data from the 2850. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX Input. RS-485 function select. When this pin is pulled high, normal -RTS function is selected. RS-485 direction control can be activated by connecting this pin to GND. This pin is wired Or-ed with FCTR Bit-3. -RTS A-B 32,24 36,27 33,22 O RX A-B 10,9 11,10 5,4 I TX A-B 11,12 13,14 7,8 O -RSCTL - - 37 I Rev. 1.00P 7 XR16C2850 GENERAL DESCRIPTION The XR16C2850 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The XR16C2850 represents such an integration with greatly enhanced features. The 2850 is fabricated with an advanced CMOS process. The 2850 is an upward solution that provides 128 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16C2550. The 2850 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 2850 by the larger transmit and receive FIFO. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 128 byte FIFO in the 2850, the data buffer will not require unloading/loading for 12.2 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the programmable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multichannel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. Rev. 1.00P 8 The 2850 provides RS-485 half dulpex control signal to select the external transceiver direction. Auto RS485 control pin (-RTS) is not activated after reset. To activate the direction control function, user has to set EFR Bit-4, and FCTR Bit-3 to 1. The -RTS pin is normally high for receive mode and it will go low when transmitter starts transmitting data. FUNCTIONAL DESCRIPTIONS UART A-B Functions The UART provides the user with the capability to Bidirectionally transfer information between an external CPU and an external serial communication device. A logic 0 on chip select pins -CSA and/or -CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 2 below. Table 2, SERIAL PORT SELECTION GUIDE CHIP SELECT -CS A-B = 1s -CS A = 0 -CS B = 0 Internal Registers The 2850 provides 15 internal registers for monitoring and control. These resisters are shown in Table 3. Twelve registers are similar to those already available in the standard 16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers, (LCR/ LSR), modem status and control registers (MCR/ MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR). Beyond the general 16C2550 features and capabilities, the 2850 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register functions are more fully described in the following paragraphs. Function None UART CHANNEL A UART CHANNEL B XR16C2850 Table 3, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Status Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *3 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Enhanced Register Set (EFR, Xon/off 1-2): Note *4 0 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 FIFO Trigger Register Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word FIFO trigger counter Feature Control Register Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word Enhanced Mode Select Register Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1. Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to BF (HEX). Rev. 1.00P 9 XR16C2850 FIFO Operation The 128 byte transmit and receive data FIFO are enabled by the FIFO Control Register (FCR) bit-0. With 16C2550 devices, the user can set the receive trigger level but not the transmit trigger level. The 2850 provides independent trigger levels for both receiver and transmitter. To remain compatible with ST16C2550, the transmit interrupt trigger level is set to 16 following a reset. It should be noted that the user can set the transmit trigger levels by writing to the FCR register, but activation will not take place until EFR bit4 is set to a logic 1. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (see hardware flow control for a description of this timing). Hardware Flow Control When automatic hardware flow control is enabled, the 2850 monitors the -CTS pin for a remote buffer overflow indication and controls the -RTS pin for local buffer overflows. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to a logic 1. If -CTS transitions from a logic 0 to a logic 1 indicating a flow control request, ISR bit-5 will be set to a logic 1 (if enabled via IER bit 6-7), and the 2850 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the -CTS input returns to a logic 0, indicating more data may be sent. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The -RTS pin will not be forced to a logic 1 (RTS Off), until the receive FIFO reaches the next trigger level. The -RTS pin will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the programmed trigger level. Under the above described conditions the 2850 will continue to accept data until the receive FIFO is full. Example of 650 trigger level selection Selected INT Trigger Pin Level Activation (characters) 8 16 24 28 8 16 24 28 -RTS Logic 1 (characters) 16 24 28 28 -RTS Logic 0 (characters) 0 8 16 24 Rev. 1.00P 10 XR16C2850 Software Flow Control When software flow control is enabled, the 2850 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2850 will halt transmission (TX) as soon as the current character(s) has completed transmission. When a match occurs, the receive ready (if enabled via Xoff IER bit-5) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters values, the 2850 will monitor the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 2850 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 2850 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the 2850 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 2850 sends the Xoff-1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the 2850 will transmit the programmed Xon-1,2 characters as soon as receive data drops below the programmed trigger level. Special Feature Software Flow Control A special feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character is detected, it will be placed on the user accessible data stack along with Rev. 1.00P 11 normal incoming RX data. This condition is selected in conjunction with EFR bits 0-3. Note that software flow control should be turned off when using this special mode by setting EFR bit 0-3 to a logic 0. The 2850 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character (see Figure 9). Although the Internal Register Table shows each XRegister with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. Time-out Interrupts Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER bits 5-7. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the 2850 will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/ RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-0). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 2850 FIFO may hold more characters than the programmed trigger level. Follow- XR16C2850 ing the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times. Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out example: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1)] = 4 characters. Programmable Baud Rate Generator The 2850 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The 2850 can support a standard data rate of 921.6Kbps. A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The 2850 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant 22-33 pF load) is connected Rev. 1.00P 12 externally between the XTAL1 and XTAL2 pins, with an external 1 M resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. The generator divides the input 16X clock by any divisor from 1 to 216 -1. The 2850 divides the basic crystal or external clock by 16. Further division of this 16X clock provides two table rates to support low and high data rate applications using the same system design. The two rate tables are selectable through the internal register, MCR bit-7. Setting MCR bit-7 to a logic 1 provides an additional divide by 4 whereas, setting MCR bit-7 to a logic 0 only divides by 1 (see Table 4 and Figure 11). The frequency of the BAUDOUT output pin is exactly 16X (16 times) of the selected baud rate (-BAUDOUT =16 x Baud Rate). Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Crystal oscillator connection XTAL1 XTAL2 R1 50-120 R2 1M X1 1.8432 MHz C2 33pF C1 22pF XR16C2850 Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 4 below, shows the two selectable baud rate tables available when using a 7.3728 MHz crystal. Table 4, BAUD RATE GENERATOR PROGRAMMING TABLE (7.3728 MHz CLOCK): Output Baud Rate MCR BIT-7=1 50 75 150 300 600 1200 2400 4800 7200 9600 19.2k 38.4k 57.6k 115.2k Output Baud Rate MCR Bit-7=0 200 300 600 1200 2400 4800 9600 19.2K 28.8K 38.4k 76.8k 153.6k 230.4k 460.8k User 16 x Clock Divisor (Decimal) 2304 1536 768 384 192 96 48 24 16 12 6 3 2 1 User 16 x Clock Divisor (HEX) 900 600 300 180 C0 60 30 18 10 0C 06 03 02 01 DLM Program Value (HEX) 09 06 03 01 00 00 00 00 00 00 00 00 00 00 DLL Program Value (HEX) 00 00 00 80 C0 60 30 18 10 0C 06 03 02 01 Figure 11, Baud Rate Generator Circuitry XTAL1 XTAL2 Clock Oscillator Logic Divide by 1 logic Divide by 4 logic MCR Bit-7=0 Baudrate Generator Logic MCR Bit-7=1 -BAUDOUT Rev. 1.00P 13 XR16C2850 DMA Operation The 2850 FIFO trigger level provides additional flexibility to the user for block mode operation. LSR bits 56 provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3). When the transmit and receive FIFO are enabled and the DMA mode is deactivated (DMA Mode 0), the 2850 activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the 2850 sets the interrupt output pin when characters in the transmit FIFO are below the transmit trigger level, or the characters in the receive FIFO are above the receive trigger level. Sleep Mode The 2850 is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. With EFR bit-4 and IER bit-4 enabled (set to a logic 1), the 2850 enters the sleep mode but resumes normal operation when a start bit is detected, a change of state on any of the modem input pins RX, -RI, -CTS, -DSR, -CD, or transmit data is provided by the user. If the sleep mode is enabled and the 2850 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. In any case, the sleep mode will not be entered while an interrupt(s) is pending. The 2850 will stay in the sleep mode of operation until it is disabled by setting IER bit4 to a logic 0. Loopback Mode The internal loopback capability allows onboard diagnostics. In the loopback mode the normal modem interface pins are disconnected and reconfigured for loopback internally. In this mode MSR bits 4-7 are also disconnected. However, MCR register bits 0-3 can be used for controlling loopback diagnostic testing. In the loopback mode, OP1 and OP2 in the MCR register Rev. 1.00P 14 (bits 0-1) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (see Figure 12). The -CTS, -DSR, CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to -DTR, -RTS, -OP1 and -OP2. Loopback test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. In this mode , the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using the lower four bits of the Modem Control Register (MCR bits 0-3) instead of the four Modem Status Register bits 4-7. The interrupts are still controlled by the IER. XR16C2850 Figure 12, Internal Loopback Mode Diagram Flow Control Logic Receive FIFO Registers I n te r C o n n e c t B u s L in e s & C o n tr o l s ig n a ls Ir Encoder Receive Shift Register MCR Bit-4=1 RX A/B -RTS A/B -CD A/B -DTR A-D -RI A/B (-OP1 A/B) -DSR A/B -OP2 A/B -CTS A/B D0-D7 -IOR,-IOW RESET A0-A2 -CS A/B Register Select Logic Data bus & Control Logic Transmit FIFO Registers Transmit Shift Register TX A/B Flow Control Logic Ir Decoder XTAL1 XTAL2 Rev. 1.00P 15 Clock & Baud Rate Generator Modem Control Logic INT A/B -RXRDY -TXRDY Interrupt Control Logic XR16C2850 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the fifteen 2850 internal registers. The assigned bit functions are more fully defined in the following paragraphs. XR16C2850 ACCESSIBLE REGISTERS A2 A1 A0 Register [Default] Note *5 BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 General Register Set 0 0 0 0 0 0 0 0 1 RHR [XX] THR [XX] IER [00] bit-7 bit-7 0/ -CTS interrupt RCVR trigger (MSB) 0/ FIFOs enabled divisor latch enable Clock select 0/ FIFO error -CD bit-7 bit-6 bit-6 0/ -RTS interrupt RCVR trigger (LSB) 0/ FIFOs enabled set break 0/ IRRT enable THR & TSR empty -RI bit-6 bit-5 bit-5 0/ Xoff interrupt 0/TX trigger (MSB) 0/ -RTS, -CTS set parity 0/ Xon Any THR empty -DSR bit-5 bit-4 bit-4 0/ Sleep mode 0/TX trigger (LSB) 0/ Xoff even parity loop back break interrupt -CTS bit-4 bit-3 bit-3 modem status interrupt DMA mode select int priority bit-2 parity enable INT Enable framing error delta -CD bit-3 bit-2 bit-2 receive line status interrupt XMIT FIFO reset int priority bit-1 stop bits -OP1 bit-1 bit-1 transmit holding register RCVR FIFO reset int priority bit-0 word length bit-1 -RTS bit-0 bit-0 receive holding register FIFO enable int status word length bit-0 -DTR 0 1 0 FCR [00] 0 1 0 ISR [01] 0 1 1 LCR [00] 1 0 0 MCR [00] 1 0 1 LSR [60] parity error delta -RI bit-2 overrun error delta -DSR bit-1 receive data ready delta -CTS bit-0 1 1 1 1 0 1 MSR [00] SCPAD [FF] Special Register Set: Note *3 0 0 0 0 0 1 DLL [00] DLM [00] bit-7 bit-15 bit-6 bit-14 bit-5 bit-13 bit-4 bit-12 bit-3 bit-11 bit-2 bit-10 bit-1 bit-9 bit-0 bit-8 Rev. 1.00P 16 XR16C2850 A2 A1 A0 Register [Default] Note *5 BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 Enhanced Register Set: Note *4 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 Xon-1[00] Xon-2[00] Xoff-1[00] Xoff-2[00] TRG [00] FCTR [00] bit-7 bit-15 bit-7 bit-15 Trig/ FC Rx/Tx Mode Auto -CTS bit-6 bit-14 bit-6 bit-14 Trig/ FC SCPAD Swap Auto -RTS bit-5 bit-13 bit-5 bit-13 Trig/ FC Trig Bit-1 Special Char. select bit-4 bit-12 bit-4 bit-12 Trig/ FC Trig Bit-0 Enable IER Bits 4-7, ISR, FCR Bits 4-5, MCR Bits 5-7 Not Used bit-3 bit-11 bit-3 bit-11 Trig FC RS485 Auto control Cont-3 Tx,Rx Control bit-2 bit-10 bit-2 bit-10 Trig/ FC IrRx Inv. Cont-2 Tx,Rx Control bit-1 bit-9 bit-1 bit-9 Trig/ FC -RTS Delay Bit-1 Cont-1 Tx,Rx Control bit-0 bit-8 bit-0 bit-8 Trig/ FC -RTS Delay Bit-0 Cont-0 Tx,Rx Control 0 1 0 EFR [00] 1 1 1 EMSR [00] Not Used Not Used Not Used Not Used Not Used ALT. Rx/Tx FIFO Count Rx/-Tx FIFO Count Note *3: The Special Register Set is accessible only when LCR bit-7 is set to a logic 1. Note *4: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to BF Hex. Note *5: The value represents the registers initialized HEX value. An X signifies a 4-bit un-initialized nibble. Rev. 1.00P 17 XR16C2850 Transmit and Receive Holding Register The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the 2850 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time, the start bit is sampled, and if it is still a logic 0, it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. DEVICE IDENTIFICATION The XR16C2850 provides a Device Identification and Device Revision code to distinguish the part from others. To read the identification number from the part, its is required to set the baud rate generator divisor latch to 1 and then set the content of the baud rate generator DLL and DLM registers to 0. Reading the content of the DLM will provide 12 hex for XR16C2850 part and reading the content of the DLL will provide the revision of the part. Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the 2850 INT output pin. Rev. 1.00P 18 IER Vs Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B) FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C) The data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. IER Vs Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1, resetting IER bits 0-3 enables the 2850 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO. B) LSR BIT 1-4 will indicate if an overrun error occurred. C) LSR BIT-5 will indicate when the transmit FIFO is empty. D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty. E) LSR BIT-7 will indicate any FIFO data errors. XR16C2850 IER BIT-0: Logic 0 = Disable the receiver ready interrupt (normal default condition). Logic 1 = Enable the receiver ready interrupt. IER BIT-1: Logic 0 = Disable the transmitter empty interrupt (normal default condition). Logic 1 = Enable the transmitter empty interrupt. IER BIT-2: Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt. IER BIT-3: Logic 0 = Disable the modem status register interrupt (normal default condition). Logic 1 = Enable the modem status register interrupt. IER BIT -4: Logic 0 = Disable sleep mode (normal default condition). Logic 1 = Enable sleep mode. See Sleep Mode section for details. IER BIT-5: Logic 0 = Disable the software flow control, receive Xoff interrupt (normal default condition). Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. IER BIT-6: Logic 0 = Disable the RTS interrupt (normal default condition). Logic 1 = Enable the RTS interrupt. The 2850 issues an interrupt when the RTS pin transitions from a logic 0 to a logic 1. IER BIT-7: Logic 0 = Disable the CTS interrupt (normal default condition). Logic 1 = Enable the CTS interrupt. The 2850 issues an interrupt when CTS pin transitions from a logic 0 to a logic 1. FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: DMA MODE Mode 0 Set and enable the interrupt for each single transmit or receive operation, and is similar to the ST16C450 mode. Transmit Ready (-TXRDY) will go to a logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (-RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. Mode 1 Set and enable the interrupt in a block mode operation. The transmit interrupt is set when the transmit FIFO is below the programmed trigger level. -TXRDY remains a logic 0 as long as one empty FIFO location is available. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However the FIFO continues to fill regardless of the programmed level until the FIFO is full. -RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. FCR BIT-0: Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. This bit must be a 1 when other FCR bits are written to or they will not be programmed. FCR BIT-1: Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT-2: Logic 0 = No FIFO transmit reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift regis- Rev. 1.00P 19 XR16C2850 ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT-3: Logic 0 = Set DMA mode 0 (normal default condition). Logic 1 = Set DMA mode 1. Transmit operation in mode 0: When the 2850 is in the ST16C450 mode (FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3 = logic 0) and when there are no characters in the transmit FIFO or transmit holding register, the -TXRDY pin will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode 0: When the 2850 is in mode 0 (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode 1: When the 2850 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode 1: When the 2850 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. FCR BIT 4-5: (logic 0 or cleared is the default condition, TX trigger level = none) The XR16C2850 provide 4 user selectable trigger levels. The FCTR Bits 4-5 selects one of the following tables. These bits are used to set the trigger level for the transmit FIFO interrupt. The XR16C2850 will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Rev. 1.00P 20 TRIGGER TABLE-A (Transmit) Default setting after reset ST16C550 mode BIT-5 X BIT-4 X FIFO trigger level None TRIGGER TABLE-B (Transmit) BIT-5 0 0 1 1 BIT-4 0 1 0 1 FIFO trigger level 16 8 24 30 TRIGGER TABLE-C (Transmit) BIT-5 0 0 1 1 BIT-4 0 1 0 1 FIFO trigger level 8 16 32 56 TRIGGER TABLE-D (Transmit) BIT-5 X BIT-4 X FIFO trigger level User programmable Trigger levels FCR BIT 6-7: (logic 0 or cleared is the default condition, RX trigger level =8) These bits are used to set the trigger level for the receiver FIFO interrupt. The FCTR Bits 4-5 selects one of the following table. XR16C2850 TRIGGER TABLE-A (Receive) Default setting after reset ST16C550 mode BIT-7 0 0 1 1 BIT-6 0 1 0 1 FIFO trigger level 1 4 8 14 Interrupt Status Register (ISR) The 2850 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table. Table 6, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: TRIGGER TABLE-B (Receive) BIT-7 0 0 1 1 BIT-6 0 1 0 1 FIFO trigger level 8 16 24 28 TRIGGER TABLE-C (Receive) BIT-7 0 0 1 1 BIT-6 0 1 0 1 FIFO trigger level 8 16 56 60 TRIGGER TABLE-D (Receive) BIT-7 X BIT-6 X FIFO trigger level User programmable Trigger levels Rev. 1.00P 21 XR16C2850 Table 6, INTERRUPT SOURCE TABLE Priority Level 1 2 2 3 4 5 6 [ ISR BITS ] Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time out) TXRDY ( Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xoff signal)/ Special character CTS, RTS change of state ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (normal default condition). ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Interrupt Source Table). ISR BIT 4-5: (logic 0 or cleared is the default condition) These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that matching Xoff character(s) have been detected. ISR bit-5 indicates that CTS, RTS have been generated. Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until Xon character(s) are received. ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Rev. 1.00P 22 LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. BIT-1 0 0 1 1 BIT-0 0 1 0 1 Word length 5 6 7 8 LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 Word length Stop bit length (Bit time(s)) 1 1-1/2 2 0 1 1 5,6,7,8 5 6,7,8 XR16C2850 LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1s in the transmitted. The receiver must be programmed to check the same format. LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced (normal default condition). LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR Bit-3 0 1 1 1 1 LCR Bit-4 X 0 1 0 1 LCR Bit-5 X 0 0 1 1 Parity selection No parity Odd parity Even parity Force parity 1 Forced parity 0 Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch and enhanced feature register enabled. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1 (normal default condition). Logic 1 = Force -DTR output to a logic 0. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1 (normal default condition). Logic 1 = Force -RTS output to a logic 0. Automatic RTS may be used for hardware flow control by enabling EFR bit-6 (see EFR bit-6). MCR BIT-2: Internal loop back mode only. Logic 0 = Set -OP1 output to a logic 1. (normal default condition) Logic 1 = Set -OP1 output to a logic 0. MCR BIT-3: Logic 0 = Forces INT outputs to three state mode (normal default condition). Logic 1 = Forces the INT outputs to the active mode. MCR BIT-4: Logic 0 = Disable loopback mode (normal default condition). Logic 1 = Enable local loopback mode (diagnostics). MCR BIT-5: Logic 0 = Disable Xon-Any function (for 16C550 compatibility, normal default condition). LCR BIT-6: When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition (normal default condition). Rev. 1.00P 23 XR16C2850 Logic 1 = Enable Xon-Any function. In this mode, any RX character received will enable Xon. MCR BIT-6: Logic 0 = Enable Modem receive and transmit input/ output interface (normal default condition). Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ Inputs are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. MCR BIT-7: Logic 0 = Divide by one. The input clock (crystal or external) is divided by sixteen and then presented to the Programmable Baud Rate Generator (BGR) without further modification, i.e., divide by one (normal, default condition). Logic 1 = Divide by four. The divide by one clock described in MCR bit-7 equals a logic 0, is further divided by four (also see Programmable Baud Rate Generator section). Line Status Register (LSR) This register provides the status of data transfers between. the 2850 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO (normal default condition). Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR BIT-1: Logic 0 = No overrun error (normal default condition). Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO; therefore, the data in the FIFO is not corrupted by the error. LSR BIT-2: Logic 0 = No parity error (normal default condition). Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. LSR BIT-3: Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO. LSR BIT-4: Logic 0 = No break condition (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. LSR BIT-5: This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. LSR BIT-6: This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. Rev. 1.00P 24 XR16C2850 LSR BIT-7: Logic 0 = No Error (normal default condition). Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read and there are no subsequent errors in the FIFO. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the 2850 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition). Logic 1 = The -CTS input to the 2850 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change (normal default condition). Logic 1 = The -DSR input to the 2850 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-2: Logic 0 = No -RI Change (normal default condition). Logic 1 = The -RI input to the 2850 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic 0 = No -CD Change (normal default condition). Logic 1 = Indicates that the -CD input has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-4: -CTS functions as hardware flow control signal input if it is enabled via EFR bit-7. The transmit holding register flow control is enabled/disabled by MSR bit-4. Rev. 1.00P 25 Flow control, when enabled, allows the starting and stopping of the transmissions based on the external modem -CTS signal. A logic 1 at the -CTS pin will stop 2850 transmissions as soon as current character has finished transmission. Normally MSR bit-4 bit is the compliment of the -CTS input. However, in the loopback mode, this bit is equivalent to the RTS bit in the MCR register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loopback mode, this bit is equivalent to the DTR bit in the MCR register. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loopback mode this bit is equivalent to the OP1 bit in the MCR register. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loopback mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The XR16C2850 provides a temporary data register to store 8 bits of user information. Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits-0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected (see Table 7), the double 8-bit words are concatenated into two sequential characters. EFR BIT 0-3: (logic 0 or cleared is the default condition) Combinations of software flow control can be selected by programming these bits. XR16C2850 Table 7, SOFTWARE FLOW CONTROL FUNCTIONS Cont-3 0 1 0 1 X X X 1 0 1 0 Cont-2 0 0 1 1 X X X 0 1 1 0 Cont-1 X X X X 0 1 0 1 1 1 1 Cont-0 X X X X 0 0 1 1 1 1 1 TX, RX software flow controls No transmit flow control Transmit Xon1/Xoff1 Transmit Xon2/Xoff2 Transmit Xon1 and Xon2/Xoff1 and Xoff2 No receive flow control Receiver compares Xon1/Xoff1 Receiver compares Xon2/Xoff2 Transmit Xon1/ Xoff1. Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Transmit Xon2/Xoff2 Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 Transmit Xon1 and Xon2/Xoff1 and Xoff2 Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 No transmit flow control Receiver compares Xon1 and Xon2/Xoff1 and Xoff2 EFR BIT-4: Enhanced function control bit. The content of the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 can be modified and latched. After modifying any bits in the enhanced registers, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents existing software from altering or overwriting the 2850 enhanced functions. Logic 0 = disable/latch enhanced features. IER bits 47, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved to retain the user settings, then IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are initialized to the default values shown in the Internal Resister Table. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0, to be compatible with ST16C550 mode (normal default condition). Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the 2850 are enabled and user settings stored during a reset will be restored. Rev. 1.00P 26 EFR BIT-5: Logic 0 = Special Character Detect Disabled (normal default condition). Logic 1 = Special Character Detect Enabled. The 2850 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special characters. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software flow control must be disabled (EFR bits 0-3 must be set to a logic 0). EFR BIT-6: Automatic RTS may be used for hardware flow control by enabling EFR bit-6. When AUTO RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and -RTS will go to a logic 1 at the next trigger level. -RTS will return to a logic 0 when data is unloaded below the next lower trigger level (Programmed trigger level -1). The state of this register bit changes with the status of the XR16C2850 hardware flow control. -RTS functions normally when hardware flow control is disabled. 0 = Automatic RTS flow control is disabled (normal default condition). 1 = Enable Automatic RTS flow control. EFR bit-7: Automatic CTS Flow Control. Logic 0 = Automatic CTS flow control is disabled (normal default condition). Logic 1 = Enable Automatic CTS flow control. Transmission will stop when -CTS goes to a logic 1. Transmission will resume when the -CTS pin returns to a logic 0. FEATURE CONTROL REGISTER This register controls the XR16C2850 new functions that are not available on ST16C550 or ST16C650. FCTR BIT 0-1: User selectable -RTS hysterisis for hardware flow control application. After reset, these bits are set to 0 to select the next trigger level for hardware flow control. FCTR Bit-1 0 0 1 1 FCTR Bit-0 0 1 0 1 Trigger level Next trigger level 4 word+trigger level 6 word+trigger level 8 word+trigger level FCTR BIT-3: Interrupt type select and Auto RS-485 half duplex control. 0 = Standard ST16C550 mode. Transmitter generates interrupt when transmit holding register is empty and transmit shift register is shifting data out. 1 = Transmit empty interrupt. Transmit interrupt is generated when the transmitter holding and shift register is empty. The -RTS A/B out pins will stay high during receive mode and will go low during transmit mode. FCTR BIT 4-5: Transmit / receive trigger table select. FCTR Bit-5 0 0 1 1 FCTR Bit-4 0 1 0 1 Table Table-A (TX/RX) Table-B (TX/RX) Table-C (TX/RX) Table-D (TX/RX) FCTR BIT-6: Register mode select. 0 = Scratch Pad register is selected as general read and write register (ST16C550 compatible mode). 1 = FIFO count register. Number of characters in transmit or receive holding register can be read via scratch pad register when this bit is set. FCTR BIT-7: Programmable trigger register select. 0 = Receiver programmable trigger level register is selected. 1 = Transmitter programmable trigger level register is selected. FCTR BIT-2: 0 = Select RX input as encoded IrDa data. 1 = Select RX input as active high encoded IrDa data. Rev. 1.00P 27 XR16C2850 TRIGGER LEVEL / FIFO DATA COUNT REGISTER User programmable transmit / receive trigger level register. TRG BIT 0-7: Write only. These bits are used to program desire trigger levels that are not available in standard tables. TRG BIT 0-7: Read only. Transmit / receive FIFO count. Number of characters in transmit or receive FIFO can be read via this register. ENHANCED MODE SELECT REGISTER This register is accessible only when FCTR Bit-6 is set to 1. EMSR BIT-0: Write only 0 = Receive FIFO count register. The scratch pad register is used to provide the receive FIFO count when it is read. 1 = Transmit FIFO count register. The scratch pad register is used to provide the transmit FIFO count when it is read. EMSR BIT-1: Write only 0 = Normal. 1 = Alternate receive - transmit FIFO count. When EMSR Bit-0=1 and EMSR Bit=1, scratch pad register is used to provide the receive - transmit FIFO count when it is read every alternate read cycle. The TRG Bit-7 will provide the FIFO count mode information, TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit mode. EMSR BIT 4-7: Reserved for future use. XR16C2850 EXTERNAL RESET CONDITIONS REGISTERS IER ISR LCR, MCR LSR MSR FCR, EFR FCTR EMSR RESET STATE IER BITS 0-7 = logic 0 ISR BIT-0=1, ISR BITS 1-7 = logic 0 BITS 0-7 = logic 0 LSR BITS 0-4 = logic 0, LSR BITS 5-6 = logic 1 LSR, BIT 7 = logic 0 MSR BITS 0-3 = logic 0, MSR BITS 4-7 = logic levels of the input signals BITS 0-7 = logic 0 BITS 0-7= logic 0 BITS 0-7 = logic 0 SIGNALS TX -OP2 -RTS -DTR -RXRDY -TXRDY INT RESET STATE Logic 1 Logic 1 Logic 1 Logic 1 Logic 1 Logic 0 Logic 0 Rev. 1.00P 28 XR16C2850 AC ELECTRICAL CHARACTERISTICS TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max 17 5 10 35 0 40 10 40 0 40 20 5 8 Limits 5.0 Min Max 17 0 10 25 0 30 10 25 0 30 15 5 24 Units Conditions T1w,T2w T3w T6s T7d T7w T7h T9d T12d T12h T13d T13w T13h T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T25d T26d T27d T28d TR N Clock pulse duration Oscillator/Clock frequency Address setup time -IOR delay from chip select -IOR strobe width Chip select hold time from -IOR Read cycle delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select hold time from -IOW Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt Delay from stop to set -RxRdy Delay from -IOR to reset -RxRdy Delay from -IOW to set -TxRdy Delay from start to reset -TxRdy Reset pulse width Baud rate devisor 35 25 25 15 50 40 40 1 45 45 24 45 1 45 45 8 216-1 40 35 35 1 40 40 24 40 1 40 40 8 216-1 ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rclk ns ns Rclk ns Rclk ns ns Rclk ns Rclk 100 pF load 100 pF load 100 pF load 100 pF load 8 8 40 1 40 1 Rev. 1.00P 29 XR16C2850 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40 C to +85 C -65 C to 150 C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0 - 70C (-40 - +85C for Industrial grade packages), Vcc=3.3 - 5.0 V 10% unless otherwise specified. Symbol Parameter Limits 3.3 Min Max -0.3 2.4 -0.3 2.0 0.6 VCC 0.8 0.4 2.0 10 10 1.2 30 5 Limits 5.0 Min Max -0.5 3.0 -0.5 2.2 2.4 10 10 3 100 5 0.6 VCC 0.8 VCC 0.4 Units Conditions VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL ICL I CC ISB CP Clock input low level Clock input high level Input low level Input high level Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Avg stand by current Input capacitance V V V V V V V V A A mA A pF IOL= 5 mA IOL= 4 mA IOH= -5 mA IOH= -1 mA Rev. 1.00P 30 XR16C2850 A0-A2 T6s -CSx T13d -IOW Valid Address Active T13w Active T16s T16h Data X552-WD-2 T13h T15d D0-D7 General write timing A0-A2 T6s -CS T7d -IOR T12d D0-D7 Valid Address Active T7w Active T12h Data X552-RD-1 T7h T9d General read timing Rev. 1.00P 31 XR16C2850 -IOW Active T17d -RTS -DTR Change of state Change of state -CD -CTS -DSR T18d INT Change of state Change of state T18d Active T19d Active Active -IOR Active Active Active T18d -RI Change of state X552-MD-1 Modem input/output timing T2w EXTERNAL CLOCK T3w T1w X654-CK-1 External clock timing Rev. 1.00P 32 XR16C2850 START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT RX 5 DATA BITS 6 DATA BITS 7 DATA BITS INT PARITY BIT NEXT DATA START BIT T20d Active T21d -IOR Active 16 BAUD RATE CLOCK X552-RX-1 Receive timing Rev. 1.00P 33 XR16C2850 START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT RX PARITY BIT NEXT DATA START BIT T25d -RXRDY Active Data Ready T26d -IOR Active X552-RX-2 Receive ready timing in none FIFO mode START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT RX PARITY BIT First byte that reaches the trigger level T25d Active Data Ready T26d -RXRDY -IOR Active Receive timing in FIFO mode Rev. 1.00P 34 X552-RX-3 XR16C2850 START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT TX 5 DATA BITS 6 DATA BITS 7 DATA BITS INT T23d -IOW Active PARITY BIT NEXT DATA START BIT T22d Active Tx Ready T24d Active 16 BAUD RATE CLOCK X552-TX-1 Transmit timing Rev. 1.00P 35 XR16C2850 START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT TX PARITY BIT NEXT DATA START BIT -IOW Active D0-D7 BYTE #1 T27d T28d -TXRDY Active Transmitter ready Transmitter not ready X552-TX-2 Transmit ready timing in none FIFO mode Rev. 1.00P 36 XR16C2850 START BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT TX 5 DATA BITS 6 DATA BITS 7 DATA BITS PARITY BIT -IOW Active T28d D0-D7 BYTE #128 -TXRDY T27d FIFO Full X552-TX-3 Transmit ready timing in FIFO mode Rev. 1.00P 37 XR16C2850 UART Frame Start Data Bits 1 0 1 0 0 1 1 0 Stop 1 1/2 Bit Time 3/16 Bit Time 0-1 16x clock delay 0 1 0 0 1 1 0 1 Stop X650-IR-1 TX 0 IRTX Bit Time Infrared transmit timing IRRX Bit Time RX 0 Start 1 Data Bits UART Frame Infrared receive timing Rev. 1.00P 38 XR16C2850 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1.00 40 21 E1 1 D 20 E A2 A1 B e Seating Plane A L B1 C a eA eB INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.980 0.600 0.485 MAX 0.250 0.070 0.195 0.024 0.070 0.014 2.095 0.625 0.580 MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 50.29 15.24 12.32 MAX 6.35 1.78 4.95 0.56 1.78 0.38 53.21 15.88 14.73 0.100 BSC 0.600 BSC 0.600 0.115 0 0.700 0.200 15 2.54 BSC 15.24 BSC 15.24 2.92 0 17.78 5.08 15 a Note: The control dimension is the inch column 39 XR16C2850 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D D1 2 1 44 45 x H2 45 x H1 C Seating Plane A2 B1 D D1 D3 BD 2 e D3 A1 A INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.685 0.650 0.590 MAX 0.180 0.120 ------. 0.021 0.032 0.013 0.695 0.656 0.630 MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 17.40 16.51 14.99 MAX 4.57 3.05 -----0.53 0.81 0.32 17.65 16.66 16.00 R 0.500 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045 12.70 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14 Note: The control dimension is the inch column 40 XR16C2850 48 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.0 mm, TQFP) Rev. 1.00 D D1 36 25 37 24 D1 D 48 13 1 B A2 A Seating Plane A1 INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.039 0.002 0.037 0.007 0.004 0.346 0.272 0.018 0 MAX 0.047 0.006 0.041 0.011 0.008 0.362 0.280 0.030 7 e 12 C a L MILLIMETERS MIN 1.00 0.05 0.95 0.17 0.09 8.80 6.90 0.45 0 MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10 0.75 7 0.020 BSC 0.50 BSC a Note: The control dimension is the millimeter column 41 XR16C2850 Notes 42 XR16C2850 Notes 43 XR16C2850 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 44 |
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